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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8132 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 low-cost, high-speed differential ampli?r functional block diagram ad8132 + 1 2 3 4 nc = no connect ?n +in v ocm nc v+ v +out ?ut 8 7 6 5 features high speed 350 mhz C3 db bandwidth 1200 v/ s slew rate resistor-settable gain internal common-mode feedback to improve gain and phase balance C68 db @ 10 mhz separate input to set the common-mode output voltage low distortion C99 dbc sfdr @ 5 mhz 800 load low power 10.7 ma @ 5 v power supply range +2.7 v to 5.5 v applications low power differential adc driver differential gain and differential filtering video line driver differential in/out level-shifting single-ended input to differential output driver active transformer general description the ad8132 is a low-cost differential or single-ended input to differential output ampli?r with resistor-settable gain. the ad8132 is a major advancement over op amps for driving differ- ential input adcs or for driving signals over long lines. the ad8132 has a unique internal feedback feature that provides output gain and phase matching balanced to ?8 db at 10 mhz, suppressing harmonics, and reducing radiated emi. manufactured on adi? next generation of xfcb bipolar pro- cess, the ad8132 has a ? db bandwidth of 350 mhz and delivers a differential signal with ?9 dbc sfdr at 5 mhz, despite its low cost. the ad8132 eliminates the need for a transformer with high-performance adcs, preserving the low frequency and dc information. the common-mode level of the differential output is adjustable by applying a voltage on the v ocm pin, easily level-shifting the input signals for driving single supply adcs. fast overload recovery preserves sampling accuracy. the ad8132 can also be used as a differential driver for the transmission of high-speed signals over low-cost twisted pair or coaxial cables. the feedback network can be adjusted to boost the high-frequency components of the signal. the ad8132 can be used for either analog or digital video signals or for other high- speed data transmission. the ad8132 is capable of driving either cat3 or cat5 twisted pair or coaxial with minimal line attenu- ation. the ad8132 has considerable cost and performance improvements over discrete line driver solutions. differential signal processing reduces the effects of ground noise which plagues ground referenced systems. the ad8132 can be used for differential signal processing (gain and ?tering) through- out a signal chain, easily simplifying the conversion between differential and single-ended components. the ad8132 is available in both soic and soic packages for operation over ?0 c to +85 c temperatures. frequency mhz 6 1 gain db 3 0 3 6 9 12 10 100 1k v s = 5v g = 1 v o,dm = 2v p-p r l,dm = 499 figure 1. large signal frequency response
rev. 0 C2C ad8132?pecifications p arameter conditions min typ max unit d in to out speci?ations dynamic performance ? db large signal bandwidth v out = 2 v p-p 300 350 mhz v out = 2 v p-p, g = 2 190 mhz ? db small signal bandwidth v out = 0.2 v p-p 360 mhz v out = 0.2 v p-p, g = 2 160 mhz bandwidth for 0.1 db flatness v out = 0.2 v p-p 90 mhz v out = 0.2 v p-p, g = 2 50 mhz slew rate v out = 2 v p-p 1000 1200 v/ s settling time 0.1%, v out = 2 v p-p 15 ns overdrive recovery time v in = 5 v to 0 v step, g = 2 5 ns noise/harmonic performance second harmonic v out = 2 v p-p, 1 mhz, r l,dm = 800 ? ?6 dbc v out = 2 v p-p, 5 mhz, r l,dm = 800 ? ?3 dbc v out = 2 v p-p, 20 mhz, r l,dm = 800 ? ?3 dbc third harmonic v out = 2 v p-p, 1 mhz, r l,dm = 800 ? ?02 dbc v out = 2 v p-p, 5 mhz, r l,dm = 800 ? ?8 dbc v out = 2 v p-p, 20 mhz, r l,dm = 800 ? ?7 dbc imd 20 mhz, r l,dm = 800 ? ?6 dbc ip3 20 mhz, r l,dm = 800 ? 40 dbm input voltage noise (rti) f = 0.1 mhz to 100 mhz 8 nv/ hz input current noise f = 0.1 mhz to 100 mhz 1.8 pa/ hz differential gain error ntsc, g = 2, r l,dm = 150 ? 0.01 % differential phase error ntsc, g = 2, r l,dm = 150 ? 0.10 degrees input characteristics offset voltage (rti) v os,dm = v out,dm /2; v din+ = v din = v ocm = 0 v 1.0 3.5 mv t min to t max variation 10 v/ c input bias current 37 a input resistance differential 12 m ? common-mode 3.5 m ? input capacitance 1pf input common-mode voltage ? to +6 v cmrr ? v out,dm / ? v in,cm ; ? v in,cm = 1 v; ?0 ?0 db resistors matched to 0.01% output characteristics output voltage swing maximum ? v out ; single-ended output ?.6 to +3.6 v output current 70 ma output balance error ? v out,cm / ? v out,dm ; ? v out,dm = 1 v ?0 db v ocm to out speci?ations dynamic performance ? db bandwidth ? v ocm = 600 mv p-p 210 mhz slew rate ? v ocm = ? v to +1 v 400 v/ s dc performance input voltage range 3.6 v input resistance 150 k ? input offset voltage v os,cm = v out,cm ; v din+ = v din = v ocm = 0 v 1.5 7mv input bias current 0.5 a v ocm cmrr [? v out,dm / ? v ocm ]; ? v ocm = 1 v; ?8 db resistors matched to 0.01% gain ? v out,cm / ? v ocm ; ? v ocm = 1 v 0.985 1 1.015 v/v power supply operating range 1.35 5.5 v quiescent current v din+ = v din = v ocm = 0 v 11 12 13 ma t min to t max variation 16 a/ c power supply rejection ratio ? v out,dm / ? v s ; ? v s = 1 v ?0 ?0 db operating temperature range 40 +85 c speci?ations subject to change without notice. (@ 25 c, v s = 5 v, v ocm = 0 v, g = 1, r l,dm = 499 , r f = r g = 348 unless otherwise noted. for g = 2, r l,dm = 200 , r f = 1000 , r g = 499 . refer to tpc 1 and tpc 10 for test setup and label descriptions. all speci?ations refer to single-ended input and differential outputs unless otherwise noted.)
rev. 0 C3C ad8132 p arameter conditions min typ max unit d in to out speci?ations dynamic performance ? db large signal bandwidth v out = 2 v p-p 250 300 mhz v out = 2 v p-p, g = 2 180 mhz ? db small signal bandwidth v out = 0.2 v p-p 360 mhz v out = 0.2 v p-p, g = 2 155 mhz bandwidth for 0.1 db flatness v out = 0.2 v p-p 65 mhz v out = 0.2 v p-p, g = 2 50 mhz slew rate v out = 2 v p-p 800 1000 v/ s settling time 0.1%, v out = 2 v p-p 20 ns overdrive recovery time v in = 2.5 v to 0 v step, g = 2 5 ns noise/harmonic performance second harmonic v out = 2 v p-p, 1 mhz, r l,dm = 800 ? ?7 dbc v out = 2 v p-p, 5 mhz, r l,dm = 800 ? ?00 dbc v out = 2 v p-p, 20 mhz, r l,dm = 800 ? ?4 dbc third harmonic v out = 2 v p-p, 1 mhz, r l,dm = 800 ? ?00 dbc v out = 2 v p-p, 5 mhz, r l,dm = 800 ? ?9 dbc v out = 2 v p-p, 20 mhz, r l,dm = 800 ? ?7 dbc imd 20 mhz, r l,dm = 800 ? ?6 dbc ip3 20 mhz, r l,dm = 800 ? 40 dbm input voltage noise (rti) f = 0.1 mhz to 100 mhz 8 nv/ hz input current noise f = 0.1 mhz to 100 mhz 1.8 pa/ hz differential gain error ntsc, g = 2, r l,dm = 150 ? 0.025 % differential phase error ntsc, g = 2, r l,dm = 150 ? 0.15 degree input characteristics offset voltage (rti) v os,dm = v out,dm /2; v din+ = v din = v ocm = 2.5 v 1.0 3.5 mv t min to t max variation 6 v/ c input bias current 37 a input resistance differential 10 m ? common-mode 3 m ? input capacitance 1pf input common-mode voltage ? to +4 v cmrr ? v out,dm / ? v in,cm ; ? v in,cm = 1 v; ?0 ?0 db resistors matched to 0.01% output characteristics output voltage swing maximum ? v out ; single-ended output 1 to 3.7 v output current 50 ma output balance error ? v out,cm / ? v out,dm ; ? v out,dm = 1 v ?8 db v ocm to out speci?ations dynamic performance ? db bandwidth ? v ocm = 600 mv p-p 210 mhz slew rate ? v ocm = 1.5 v to 3.5 v 340 v/ s dc performance input voltage range 1 to 3.7 v input resistance 130 k ? input offset voltage v os,cm = v out,cm ; v din+ = v din = v ocm = 2.5 v 5 11 mv input bias current 0.5 a v ocm cmrr [? v out,dm / ? v ocm ]; ? v ocm = 2.5 1 v; ?6 db resistors matched to 0.01% gain ? v out,cm / ? v ocm ; ? v ocm = 2.5 1 v 0.985 1 1.015 v/v power supply operating range 2.7 11 v quiescent current v din+ = v din = v ocm = 2.5 v 9.4 10.7 12 ma t min to t max variation 10 a/ c power supply rejection ratio ? v out,dm / ? v s ; ? v s = 1 v ?0 ?0 db operating temperature range 40 +85 c speci?ations subject to change without notice. (@ 25 c, v s = 5 v, v ocm = 2.5 v, g = 1, r l,dm = 499 , r f = r g = 348 unless otherwise noted. for g = 2, r l,dm = 200 , r f = 1000 , r g = 499 . refer to tpc 1 and tpc 10 for test setup and label descriptions. all speci?ations refer to single-ended input and differential outputs unless otherwise noted.) ad8132?pecifications
rev. 0 C4C ad8132?pecifications p arameter conditions min typ max unit d in to out speci?ations dynamic performance ? db large signal bandwidth v out = 1 v p-p 350 mhz v out = 1 v p-p, g = 2 165 mhz ? db small signal bandwidth v out = 0.2 v p-p 350 mhz v out = 0.2 v p-p, g = 2 150 mhz bandwidth for 0.1 db flatness v out = 0.2 v p-p 45 mhz v out = 0.2 v p-p, g = 2 50 mhz noise/harmonic performance second harmonic v out = 1 v p-p, 1 mhz, r l,dm = 800 ? ?00 dbc v out = 1 v p-p, 5 mhz, r l,dm = 800 ? ?4 dbc v out = 1 v p-p, 20 mhz, r l,dm = 800 ? ?7 dbc third harmonic v out = 1 v p-p, 1 mhz, r l,dm = 800 ? ?0 dbc v out = 1 v p-p, 5 mhz, r l,dm = 800 ? ?5 dbc v out = 1 v p-p, 20 mhz, r l,dm = 800 ? ?6 dbc input characteristics offset voltage (rti) v os,dm = v out,dm /2; v din+ = v din = v ocm = 1.5 v 10 mv input bias current 3 a cmrr ? v out,dm / ? v in,cm ; ? v in,cm = 0.5 v; ?0 db resistors matched to 0.01% v ocm to out speci?ations dc performance input offset voltage v os,cm = v out,cm ; v din+ = v din = v ocm = 1.5 v 7mv gain ? v out,cm / ? v ocm ; ? v ocm = 0.5 v 1 v/v power supply operating range 2.7 11 v quiescent current v din+ = v din = v ocm = 0 v 7.25 ma power supply rejection ratio ? v out,dm / ? v s ; ? v s = 0.5 v ?0 db operating temperature range 40 +85 c speci?ations subject to change without notice. (@ 25 c, v s = 3 v, v ocm = 1.5 v, g = 1, r l,dm = 499 , r f = r g = 348 unless otherwise noted. for g = 2, r l,dm = 200 , r f = 1000 , r g = 499 . refer to tpc 1 and tpc 10 for test setup and label descriptions. all speci?ations refer to single-ended input and differential outputs unless otherwise noted.)
rev. 0 C5C ad8132 absolute maximum ratings 1, 2 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v ocm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s internal power dissipation . . . . . . . . . . . . . . . . . . . . 250 mw operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above listed in the operational section of this speci?ation is not implied. exposure to absolute maximum ratings for any extended periods may affect device reliability. 2 thermal resistance measured on semi standard 4-layer board. 8-lead soic: ja = 121 c/w 8-lead soic: ja = 142 c/w ambient temperature c 50 0 t j = 150 c 2.0 1.5 1.0 maximum power dissipation watts 8-lead soic package 40 30 0 10203040506070 8090 8-lead microsoic 0.5 20 10 figure 2. plot of maximum power dissipation vs. temperature ordering guide model temperature range package description package option AD8132AR ?0 c to +85 c 8-lead soic so-8 AD8132AR-reel 1 ?0 c to +85 c 13" tape and reel AD8132AR-reel7 2 ?0 c to +85 c 7" tape and reel AD8132ARm ?0 c to +85 c 8-lead soic sm-8 AD8132ARm-reel 3 ?0 c to +85 c 13" tape and reel AD8132ARm-reel7 2 ?0 c to +85 c 7" tape and reel ad8132-eval evaluation board notes 1 13" reels of 2500 each. 2 7" reels of 1000 each. 3 13" reels of 3000 each. pin function descriptions pin no. name function 1 ?n negative input. 2v ocm voltage applied to this pin sets the common- mode output voltage with a ratio of 1:1. for example, 1 v dc on v ocm will set the dc bias level on +out and ?ut to 1 v. 3 v+ positive supply voltage. 4 +out positive output. note: the voltage at ? in is inverted at +out. 5 ?ut negative output. note: the voltage at +d in is inverted at ?ut. 6 v negative supply voltage. 7 nc no connect. 8 +in positive input. pin configuration ad8132 + 1 2 3 4 nc = no connect in +in v ocm nc v+ v +out out 8 7 6 5 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8132 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 ad8132 C6C 0.1 f 348 348 49.9 24.9 348 348 499 cf cf tpc 1. b asic test circuit, g = 1 frequency mhz gain db 1 10 100 1k v s as shown g = 1 v o,dm = 0.2v p-p r l,dm = 499 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 v s = 3v v s = 5v v s = 5v tpc 4. 0.1 db flatness vs. frequency; c f = 0.5 pf frequency mhz gain db 1 10 100 1k 2 1 0 1 2 3 4 5 3 v s = 5v g = 1 v o,dm = 2v p-p r l,dm = 499 temperature as shown 40 c +85 c +25 c tpc 7. large signal response vs. temperature frequency mhz gain db 2 1 1 0 1 2 3 4 5 10 100 1k v s as shown g = 1 v o,dm = 0.2v p-p r l,dm = 499 v s = 3v v s = 5v v s = 5v tpc 2. small signal frequency response frequency mhz gain db 1 10 100 1k 2 1 0 1 2 3 4 5 3 v s as shown g = 1 v o,dm = 2v p-p for v s = 5v, 5v v o,dm = 1v p-p for v s = 3v r l,dm = 499 v s = 3v v s = 5v v s = 5v v s = 3v tpc 5. large signal frequency response; c f = 0 pf frequency mhz gain db 1 10 100 1k 2 1 0 1 2 3 4 5 3 v s = 5v g = 1 v o,dm = 2v p-p r l,dm = 499 r f as shown r f = 499 r f = 348 r f = 249 tpc 8. large signal frequency response vs. r f frequency mhz gain db 1 10 100 1k 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.5 v s as shown g = 1 v o,dm = 0.2v p-p r l,dm = 499 v s = 3v v s = 5v v s = 5v tpc 3. 0.1 db flatness vs. frequency; c f = 0 pf frequency mhz gain db 1 10 100 1k 2 1 0 1 2 3 4 5 v s as shown g = 1 v o,dm = 2v p-p for v s = 5v, 5v v o,dm = 1v p-p for v s = 3v r l,dm = 499 v s = 3v v s = 5v v s = 5v v s = 3v tpc 6. large signal frequency response; c f = 0.5 pf frequency mhz impedance 100 1 10 1 0.1 10 100 v s = 5v v s = 5v tpc 9. closed-loop single-ended z out vs. frequency; g = 1 typical performance characteristics
rev. 0 ad8132 C7C frequency mhz gain db 7 1 6 5 4 3 2 1 10 100 1k v s as shown g = 2 v o,dm = 0.2v p-p r l,dm = 200 v s = 3v v s = 5v, +5v tpc 11. small signal frequency response frequency mhz gain db 1 10 100 1k 7 6 5 4 3 2 1 v s = 5v g = 2 v o,dm = 0.2v p-p r l,dm = 200 r f as shown r f = 1.0k r f = 499 r f = 1.5k tpc 14. small signal frequency response vs. r f 0.1 f 49.9 24.9 r f r f r g r g r l r l g = 1: r f = r g = 348 , r l = 249 (r l,dm = 498 ) g = 2: r f = 1000 , r g = 499 , r l = 100 (r l,dm = 200 ) tpc 17. test circuit for output balance frequency mhz gain db 1 10 100 1k v s = 3v, 5v, 5v g = 2 v o,dm = 0.2v p-p r l,dm = 200 6.1 6.0 5.9 5.8 5.7 5.6 5.5 tpc 12. 0.1 db flatness vs. frequency 0.1 f 499 499 49.9 24.9 r f 200 r f tpc 15. test circuit for various gains frequency mhz rti balance error db 1 10 100 1k 25 30 35 40 45 50 55 v s = 5v gain as shown v out,dm = 2v p-p v out,cm / v out,dm 60 65 g = 1 g = 2 70 75 tpc 18. rti output balance error vs. frequency 0.1 f 499 499 49.9 24.9 1000 1000 200 tpc 10. basic test circuit, g = 2 frequency mhz gain db 1 10 100 1k 7 6 5 4 3 2 1 v s = 5v, 5v v s = 3v v s as shown g = 2 v o,dm = 2v p-p for v s = 5v, 5v v o,dm = 1v p-p for v s = 3v r l,dm = 200 tpc 13. l arge signal frequency response frequency mhz gain db 1 10 100 1k 25 20 15 10 5 0 5 v s = 5v v o, dm = 2v p-p r l, dm = 200 r g = 499 10 15 g = 10, r f = 4.99k g = 5, r f = 2.49k g = 2, r f = 1k g = 1, r f = 499 tpc 16. large signal response for various gains
rev. 0 ad8132 C8C 0.1 f 348 348 49.9 24.9 348 348 lpf 300 300 hpf z in = 50 2:1 transformer tpc 19. harmonic distortion test circuit, g = 1, r l,dm = 800 ? frequency mhz distortion dbc 0506070 40 50 60 70 80 90 100 20 30 40 10 110 r l,dm = 800 v out,dm = 1v p-p hd3 (v s = 3v) hd2 (v s = 3v) hd2 (v s = 5v) hd3 (v s = 5v) tpc 20. harmonic distortion vs. frequency, g = 1 differential output voltage v p - p distortion dbc 0 40 50 60 70 80 90 100 234 1 110 v s = 5v r l,dm = 800 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) tpc 23. harmonic distortion vs. differential output voltage, g = 1 frequency mhz distortion dbc 0506070 40 50 60 70 80 90 100 20 30 40 10 110 r l,dm = 800 v out,dm = 2v p-p hd3 (v s = 5v) hd2 (v s = 5v) hd2 (v s = 5v) hd3 (v s = 5v) 30 tpc 21. harmonic distortion vs. frequency, g = 1 differential output voltage v p - p distortion dbc 0 40 50 60 70 80 90 100 234 1 110 v s = 5v r l,dm = 800 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 56 tpc 24. harmonic distortion vs. differential output voltage, g = 1 differential output voltage v p-p distortion dbc 0.25 1.50 1.75 40 50 60 70 80 90 100 0.75 1.00 1.25 0.50 110 v s = 3v r l,dm = 800 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) /,1((

; 34# r load distortion dbc 200 700 800 50 60 70 80 90 100 400 500 600 300 110 v s = 3v v o,dm = 1v p-p 900 1000 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) tpc 25. harmonic distortion vs. r load , g = 1
rev. 0 ad8132 C9C r load distortion dbc 200 700 800 50 60 70 80 90 100 400 500 600 300 110 v s = 5v v out,dm = 2v p-p 900 1000 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) tpc 26. harmonic distortion vs. r load , g = 1 r load distortion dbc 200 700 800 50 60 70 80 90 100 400 500 600 300 110 v s = 5v v out,dm = 2v p-p hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 900 1000 tpc 27. harmonic distortion vs. r load , g = 1 0.1 f 499 499 49.9 24.9 1000 1000 lpf 300 300 hpf z in = 50 2:1 transformer tpc 28. harmonic distortion test circuit, g = 2, r l,dm = 800 ? frequency mhz distortion dbc 40 50 50 60 70 80 90 100 10 20 30 0 110 hd3 (v s = 3v) 60 70 r l,dm = 800 v out,dm = 1v p-p 40 hd3 (v s = 5v) hd2 (v s = 5v) hd2 (v s = 3v) tpc 29. harmonic distortion vs. frequency, g = 2 frequency mhz distortion dbc 40 50 50 60 70 80 90 100 10 20 30 0 hd3 (v s = 5v) 60 70 r l,dm = 800 v out,dm = 4v p-p 40 hd3 (v s = 5v) hd2 (v s = 5v) 80 30 20 hd2 (v s = 5v) tpc 30. harmonic distortion vs. frequency, g = 2 differential output voltage v p-p distortion dbc 2 50 60 70 80 90 100 1 03 v s = 5v r l,dm = 800 40 hd3 (f = 20mhz) 4 110 120 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) tpc 31. harmonic distortion vs. differential output voltage, g = 2
rev. 0 ad8132 C10C differential output voltage v p - p distortion dbc 2 50 60 70 80 90 100 1 03 v s = 5v r l,dm = 800 40 hd3 (f = 20mhz) 4 110 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 56 tpc 32. harmonic distortion vs. differential output voltage, g = 2 frequency mhz p out dbm (re:50 ) 10 19.5 0 10 20 30 40 50 60 70 80 90 20 20.5 f c = 20mhz v s = 5v r l,dm = 800 tpc 35. intermodulation distortion, g = 1 300mv 5ns v s = 3v v out,dm = 1.5v p-p c f = 0pf c f = 0.5pf tpc 38. large signal transient response, g = 1 r load distortion dbc 400 50 60 70 80 90 100 300 200 500 hd3 (f = 20mhz) 600 110 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 700 800 v s = 5v v out,dm = 2v p-p 900 1000 tpc 33. harmonic distortion vs. r load , g = 2 frequency mhz intercept dbm (re:50 ) 45 15 0 10 70 20 30 40 50 60 40 35 30 25 20 v s = 5v, 5v r l,dm = 800 tpc 36. third order intercept vs. frequency, g = 1 400mv 5ns v s = 5v v out,dm = 2v p-p c f = 0pf c f = 0.5pf tpc 39. large signal transient response, g = 1 r load distortion dbc 400 50 60 70 80 90 100 300 200 500 hd3 (f = 20mhz) 600 110 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 700 800 v s = 5v v out,dm = 2v p-p 900 1000 tpc 34. harmonic distortion vs. r load , g = 2 v s = 5v, 5v, 3v 40mv 5ns tpc 37. small signal transient response, g = 1 v s = 5v v out,dm = 2v p-p 400mv 5ns c f = 0pf c f = 0.5pf tpc 40. large signal transient response, g = 1
rev. 0 ad8132 C11C 1v 5ns v out v out+ v +din v out ,dm tpc 41. large signal transient response, g = 1 400mv 5ns v s = 5, 5v tpc 44. large signal transient response, g = 2 0.1 f 348 348 49.9 24.9 348 348 453 24.9 24.9 c l tpc 47. test circuit for cap load drive 40mv 5ns v s = 5, 5, 3v tpc 42. small signal transient response, g = 2 1v 5ns v s = 5v v out ,dm v out v out+ v +din tpc 45. large signal transient response, g = 2 5ns c l = 5pf c l = 0pf c l = 20pf 400mv tpc 48. large signal transient response for various capacitor loads 300mv 5ns v s = 3v tpc 43. large signal transient response, g = 2 2mv 5ns v s = 5v g = 1 v o ,dm = 2v p-p r l ,dm = 499 5ns/div 0.1%/div 0 5 10 15 20 25 30 35 40 /,1*0 #=% / frequency mhz psrr db 0.1 1 10 100 0 10 20 30 40 50 60 70 80 90 1000 v out,dm v s +psrr psrr +psrr (v s = 5v, 5v) psrr (v s = 5v) /,1*8 ,%"
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rev. 0 ad8132 C12C 348 348 49.9 348 348 249 249 v out,dm v out, cm note: resistors matched to 0.01%. tpc 50. cmrr test circuit v s = 5v v ocm = 1v to +1v 400mv 5ns v out,cm tpc 53. v ocm transient response frequency hz 1000 10 100 10 1 100 1k 10k 100k 1m 10m 100m 1.8pa/ hz input current noise pa/ hz tpc 56. input current noise vs. frequency frequency mhz cmrr db 1 10 100 1000 70 80 50 60 30 40 20 v out,dm v in,cm v out,cm v in,cm v s = 5v v in,cm = 2v p-p tpc 51. cmrr vs. frequency frequency mhz v ocm cmrr db 1 10 100 1000 70 80 50 60 30 40 20 v ocm = 2v p-p v ocm = 600mv p-p v out,dm v ocm 10 tpc 54. v ocm cmrr vs. frequency 5ns v out,dm (0.5v/div) v in,sm (1v/div) v s = 5v v in = 2.5v step g = 2 r f = 1k r l,dm = 200 v/div as shown tpc 57. overdrive recovery frequency mhz db 1 10 100 1000 9 12 3 6 0 v out,cm v ocm v ocm = 600mv p-p v ocm = 2v p-p 3 6 15 v s = 5v tpc 52. v ocm gain response frequency hz input voltage noise nv/ hz 1000 10 100 10 1 100 1k 10k 100k 1m 10m 8nv/ hz 100m /,1++ ! "
& temperature c supply current ma 15 13 5 50 30 90 10 10 30 50 70 11 9 7 v s = 5v v s = 5v tpc 58. quiescent current vs. temperature
rev. 0 ad8132 C13C operational description de?ition of terms ad8132 c f +in in r f c f r f r g r g +d in v ocm d in r l , dm +out v out , dm out figure 3. circuit de?nitions differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or equivalently output differential-mode voltage) is de?ed as: v out,dm = ( v +out ?v ?ut ) v +out and v ?ut refer to the voltages at the +out and out terminals with respect to a common reference. common-mode voltage refers to the average of two node volt- ages. the output common-mode voltage is de?ed as: v out,cm = ( v +out + v ?ut ) / 2 basic circuit operation one of the more useful and easy to understand ways to use the ad8132 is to provide two equal-ratio feedback networks. to match the effect of parasitics, these networks should actually be comprised of two equal-value feedback resistors, r f and two equal-value gain resistors, r g . this circuit is diagrammed in figure 3. like a conventional op amp, the ad8132 has two differential inputs that can be driven with both a differential-mode input voltage, v in,dm , and a common-mode input voltage, v in,cm . there is another input, v ocm , which is not present on conven- tional op amps, but provides another input to consider on the ad8132. it is totally separate from the above inputs. there are two complementary outputs whose response can be de?ed by a differential-mode output, v out,dm and a common- mode output, v out,cm . temperature c differential output offset mv 0 0.5 2.5 40 20 100 0 20406080 1.0 1.5 2.0 v s = 5v v s = 5v tpc 59. differential offset voltage vs. temperature table i indicates the gain from any type of input to either type of output. table i. differential and common-mode gains input v out,dm v out,cm v in,dm r f /r g 0 (by design) v in,cm 0 0 (by design) v ocm 0 1 (by design) the differential output (v out,dm ) is equal to the differential input voltage (v in,dm ) times r f /r g . in this case, it does not matter if both differential inputs are driven, or only one output is driven and the other is tied to a reference v oltage, like ground. as can be seen from the two zero entries in the ?st c olumn, neither of the common-mode inputs has any effect on this gain. the gain from v in,dm to v out,cm is 0 and to ?st order does not depend on the ratio matching of the feedback networks. the common-mode feedback loop within the ad8132 provides a corrective action to keep this gain term minimized. the term ?alance error?describes the degree to which this gain term differs from zero. the gain from v in,cm to v out,dm does directly depend on the matching of the feedback networks. the analogous term for this transfer function, which is used in conventional op amps, is ?ommon-mode rejection ratio?or cmrr. thus, if it is desirable to have a high cmrr, the feedback ratios must be well matched. the gain from v in,cm to v out,cm is also ideally 0, and is ?st- order independent of the feedback ratio matching. as in the case of v in,dm to v out,cm , the common-mode feedback loop keeps this term minimized. the gain from v ocm to v out,dm is ideally 0 only when the feed- back ratios are matched. the amount of differential output signal that will be created by varying v ocm is related to the degree of mismatch in the feedback networks. v ocm controls the output common-mode voltage v out,cm with a unity-gain transfer function. with equal-ratio feedback networks (as assumed above), its effect on each output will be the same, which is another way to say that the gain from v ocm to v out,dm is zero. if not driven, the output common-mode will be at mid- supplies. it is recommended that a 0.1 f bypass capacitor be connected to v ocm .
rev. 0 ad8132 C14C when unequal feedback ratios are used, the two gains associated with v out,dm become nonzero. this signi?antly complicates the mathematical analysis along with any intuitive understand- ing of how the part operates. some of these con?urations will be in another section. theory of operation the ad8132 differs from conventional op amps by the external presence of an additional input and output. the additional input, v ocm , controls the output common-mode voltage. the additional output is the analog complement of the single output of a conventional op amp. for its operation, the ad8132 makes use of two feedback loops as compared to the single loop of conventional op amps. while this provides signi?ant freedom to create various novel circuits, basic op amp theory can still be used to analyze the operation. one of the feedback loops controls the output common-mode voltage, v out,cm . its input is v ocm (pin 2) and the output is the common-mode, or average voltage, of the two differential outputs (+out and ?ut). the gain of this circuit is internally set to unity. when the ad8132 is operating in its linear region, this establishes one of the operational constraints: v out,cm = v ocm . the second feedback loop controls the differential operation. similar to an op amp, the gain and gain-shaping of the transfer function is controllable by adding passive feedback networks. how- ever, only one feedback network is required to ?lose the loop?and fully constrain the operation. but depending on the function desired, two feedback networks can be used. this is possible as a result of ha ving two outputs that are each in verted with respect to the differential inputs. general usage of the ad8132 several assumptions are made here for a ?st-order analysis, which are the typical assumptions used for the analysis of op amps: the input impedances are arbitrarily large and their loading effect can be ignored. the input bias currents are suf?iently small so they can be neglected. the output impedances are arbitrarily low. the open-loop gain is arbitrarily large, which drives the ampli?r to a state where the input differential voltage is effectively zero. offset voltages are assumed to be zero. while it is possible to operate the ad8132 with a purely differ- ential input, many of its applications call for a circuit that has a single-ended input with a differential output. for a single-ended-to-differential circuit, the r g of the undriven input will be tied to a reference voltage. for now this is ground, and other conditions will be discussed later. also, the voltage at v ocm , and hence v out,cm will be assumed to be ground for now. figure 4 shows a generalized schematic of such a circuit using an ad8132 with two feedback paths. for each feedback network, a feedback factor can be de?ed, which is the fraction of the output signal that is fed back to the opposite-sign input. these terms are: 1 = r g1 /(r g1 + r f1 ) 2 = r g2 /(r g2 + r f2 ) the feedback factor 1 is for the side that is driven, while the feedback factor 2 is for the side that is tied to a reference volt- age, (ground for now). note also that each feedback factor can vary anywhere between 0 and 1. a single-ended-to-differential gain equation can be derived which is true for all values of 1 and 2: g = 2 (1 1)/( 1 + 2) this expression is not very intuitive, but some further examples can provide better understanding of its implications. one obser- vation that can be made right away is that a tolerance error in 1 does not have the same effect on gain as the same tolerance error in 2. resistorless differential ampli?r (high input impedance inverting ampli?r) the simplest closed-loop circuit that can be made does not require any resistors and is shown in figure 7. in this circuit, 1 is equal to zero, and 2 is equal to one. the gain is equal to two. a more intuitive means to ?ure the gain is by simple inspec- tion. +out is connected to ?n, whose voltage is equal to the voltage at +in under equilibrium conditions. t hus, +v out is equal to v in , and there is unity gain in this path. since ?ut has to swing in the opposite direction from +out due to the common-mode constraint, its effect will double the output signal and produce a gain of two. one useful function that this circuit provides is a high input- impedance inverter. if +out is ignored, there is a unity-gain, high-input-impedance ampli?r formed from +in to ?ut. most traditional op amp inverters have relatively low input impedances, unless they are buffered with another ampli?r. v ocm has been assumed to be at midsupply. since there is still the constraint from the above discussion that +v out must equal v in , changing the v ocm voltage will not change +v out (= v in ). therefore, all of the effect of changing v ocm must show up at ?ut. for example, if v ocm is raised by 1 v, then ? out must go up by 2 v. this makes v out,cm also go up by 1 v, since it is de?ed as the average of the two differential output voltages. this means that the gain from v ocm to the differential output is two. other 2 = 1 circuits the above simple con?uration with 2 = 1 and its gain-of-two is the highest gain circuit that can be made under this condition. since 1 was equal to zero, only higher 1 values are possible. all of these circuits with higher values of 1 will have gains lower than two. however, circuits with 1 equal to one are not practical, because they have no effective input, and result in a gain of 0. to increase 1 from zero, it is necessary to add two resistors in a feedback network. a generalized circuit that has 1 with a value higher than zero is shown in figure 6. a couple of differ- ent convenient gains that can be created are a gain of 1, when 1 is equal to 1/3, and a gain of 0.5 when 1 equals 0.6. in all of these circuits with 2 equal to 1, v ocm serves as the reference voltage from which to measure the input voltage and the individual output voltages. in general, when v ocm is varied in these circuits, a differential output signal will be generated in addition to v out,cm changing the same amount as the voltage change of v ocm .
rev. 0 ad8132 C15C varying 2 while the circuit above sets 2 to 1, another class of simple circuits can be made that set 2 equal to zero. this means that there is no feedback from +out to ?n. this class of circuits is very similar to a conventional inverting op amp. however, the ad8132 circuits have an additional output and common-mode input which can be analyzed separately (see figure 8). with ?n connected to ground, +in becomes a ?irtual ground in the same sense that the term is used in conventional op amps. both inputs must maintain the same voltage for equilibrium operation, so if one is set to ground, the other will be driven to ground. the input impedance can also be seen to be equal to r g , just as in a conventional op amp. in this case, however, the positive input and negative output are used for the feedback network. since a conventional op amp does not have a negative output, only its inverting input can be used for the feedback network. the ad8132 is symmetrical, so the feedback network on either side can be used to produce the same results. since +in is a summing junction, by analogy to conventional op amps, the gain from v in to ?ut will be ? f /r g . this will hold true regardless of the voltage on v ocm . and since +out will move the same amount in the opposite direction from ?ut, the overall gain will be ? (r f /r g ). v ocm still governs v out,cm , so +out must be the only output that moves when v ocm is varied. since v out,cm is the average of the two outputs, +out must move twice as fast and in the same direction as v ocm to create the proper v out,cm . therefore, the gain from v ocm to +out must be two. in these circuits with 2 equal to zero, the gain can theoretically be set to any value from close to zero to in?ity, just as it can with a conventional op amp in the inverting mode. however, practical real-world limitations and parasitics will limit the range of acceptable gains to more modest values. 1 = 0 there is yet another class of circuits where there is no feedback from ?ut to +in. this is the case where 1 = 0. the resistor less differential ampli?r described above meets this condition, but it was presented only with the condition that 2 = 1. recall that this circuit had a gain equal to two. if 2 is decreased in this circuit from unity, a smaller part of +v out will be fed back to ?n and the gain will increase. see figure 5. this circuit is very similar to a noninverting op amp con?uration, except for the presence of the additional comple- mentary output. therefore, the overall gain is twice that of a noninverting op amp or 2 (1 + r f2 /r g2 ) or 2 (1/ 2). once again, varying v ocm will not affect both outputs in the same way, so in addition to varying v out,cm with unity gain, there will also be an affect on v out,dm by changing v ocm . estimating the output noise voltage similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +in and ?n, by the circuit noise gain. the noise gain is de?ed as: g r r n f g =+ ? ? ? ? ? ? 1 to compute the total output referred noise for the circuit of figure 3, consideration must also be given to the contribution of the resistors r f and r g . refer to table ii for estimated output noise voltage densities at various closed-loop gains. table ii. recommended resistor values and noise performance for speci? gains r g r f bandwidth output noise output noise gain ( )( ) ? db ad8132 only ad8132 + r g , r f 1 499 499 360 mhz 16 nv/ hz 17 nv/ hz 2 499 1.0 k 160 mhz 24.1 nv/ hz 26.1 nv/ hz 5 499 2.49 k 65 mhz 48.4 nv/ hz 53.3 nv/ hz 10 499 4.99 k 20 mhz 88.9 nv/ hz 98.6 nv/ hz calculating an application circuit? input impedance the effective input impedance of a circuit such as that in fig- ure 3, at +d in and d in , will depend on whether the ampli er is being driven by a single-ended or differential signal source. for balanced differential input signals, the input impedance (r in ,dm) between the inputs (+d in and d in ) is simply: r in,dm = 2 r g in the case of a single-ended input signal (for example if d in is grounded and the input signal is applied to +d in ), the input impedance becomes: r r r rr in dm g f gf , = ? + () ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 the circuit s input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . input common-mode voltage range in single supply applications the ad8132 is optimized for level-shifting ground referenced input signals. for a single-ended input this would imply, for example, that the voltage at d in in figure 3 would be zero volts when the ampli er s negative power supply voltage (at v ) was also set to zero volts. setting the output common-mode voltage the ad8132 s v ocm pin is internally biased at a voltage approxi- mately equal to the midsupply point (average value of the voltages on v+ and v ). relying on this internal bias will result in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common-mode level is required, it is recommended that an external source, or resistor divider (with r source < 10k), be used. the output common-mode offset speci ed on pages 2 and 3 assume the v ocm input is driven by a low impedance voltage s ource.
rev. 0 ad8132 C16C driving a capacitive load a purely capacitive load can react with the pin and bondwire inductance of the ad8132 resulting in high frequency ringing in the pulse response. one way to minimize this effect is to place a small capacitor across each of the feedback resistors. the added capacitance should be small to avoid destabilizing the ampli er. an alternative technique is to place a small resistor in series with the ampli er s outputs as shown in tpc 47. layout, grounding and bypassing as a high-speed part, the ad8132 is sensitive to the pcb envi ronment in which it has to operate. realizing its superior speci cations requires attention to various details of good high- speed pcb design. the rst requirement is a good solid ground plane that covers as much of the board area around the ad8132 as possible. the only exception to this is that the two input pins (pins 1 and 8) should be kept a few mm from the ground plane, and ground should be removed from inner layers and the opposite side of the board under the input pins. this will minimize the stray capacitance on these nodes and help preserve the gain flatness vs. frequency. the power supply pins should be bypassed as close as possible to the device to the nearby ground plane. good high-frequency ceramic chip capacitors should be used. this bypassing should be done with a capacitance value of 0.01 f to 0.1 f for each supply. further away, low frequency bypassing should be provided with 10 f tantalum capacitors from each supply to ground. the signal routing should be short and direct in order to avoid parasitic effects. wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. when running differential signals over a long distance, the traces on pcb should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. this will reduce the radiated energy and make the circuit less susceptible to interference. circuits r f1 + r f2 r g1 r g2 figure 4. typical four-resistor feedback circuit + r f2 r g2 v in figure 5. typical circuit with 1 = 0 r f1 + r g1 figure 6. typical circuit with 2 = 1 + v in figure 7. resistorless g = 2 circuit with 1 = 0 r f1 + r g1 v in figure 8. typical circuit with 2 = 0
rev. 0 ad8132 C17C 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 fund 2nd 3rd 4th 5th 7th 8th 9th 6th f s = 40mhz f in = 2.5mhz input frequency mhz output dbc figure 10. fft response for ad8132 driving ad9203 balanced cable driver when driving a twisted pair cable, it is desirable to drive only a pure differential signal onto the line. if the signal is purely dif- ferential (i.e., fully balanced), and the transmission line is twisted and balanced, there will be a minimum radiation of any signal. 3v 0.1 f 10 f + 3v 348 0.1 f 348 49.9 348 24.9 10k 10k 1v p-p 348 60.4 60.4 20pf 20pf ainn ainp avdd drvdd avss drvss ad9203 digital outputs 3v 0.1 f 0.1 f ad8132 figure 9. ad8132 driving ad9203, a 10-bit 40 msps a/d converter applications a/d driver many of the newer high-speed a/d converters are single-supply and have differential inputs. thus, the driver for these devices should be able to convert from a single-ended to a differential signal and provide output common-mode level-shifting in addition to having low distortion and noise. the ad8132 con- veniently performs these functions when driving the ad9203, a 10-bit, 40 msps a/d converter. in figure 9 a 1 v p-p signal drives the input of an ad8132 con gured for unity gain. both the ad8132 and the ad9203 are powered from a single 3 v supply. a voltage divider biases v ocm at midsupply, which in turn drives v out,cm to be half the supply voltage. this is within the common-mode range of the ad9203. between the a/d and the driver is a one-pole, differential lter that helps to lter some of the noise and assists the switched- capacitor inputs of the a/d. each of the a/d inputs will be driven by a 0.5 v p-p signal that goes from 1.25 v dc to 1.75 v dc. figure 10 is an fft plot of the performance of the circuit when running at a clock rate of 40 msps and an input frequency of 2.5 mhz. 499 523 1k 1k 10 f + +5v ad8132 0.1 f 49.9 50 source 0.1 f + 0.1 f 10 f 5v 49.9 49.9 twisted pair 100 1 2 3 4 7 5 ad830 + 0.1 f 10 f 5v 10 f + +5v 0.1 f v out figure 11. balanced line driver and receiver using ad8132 and ad830
rev. 0 ad8132 C18C low-pass differential filter similar to an op amp, various types of active lters can be cre- ated with the ad8132. these can have single-ended inputs and differential outputs, which can provide an antialias function when driving a differential a/d converter. figure 14 is a schematic of a low-pass, multiple-feedback lter. the active section contains two poles, and an additional pole is added at the output. the lter was designed to have a 3 db frequency of 1 mhz. the actual 3 db frequency was measured to be 1.12 mhz as shown in figure 15. 33pf 2.15k 953 953 33pf 2.15k 100pf 100pf 2k 2k 24.9 49.9 549 549 200pf 200pf v in v out figure 14. 1 mhz, 3-pole differential output low-pass multiple feedback filter frequency hz 10 10k 0 10 20 30 40 50 60 70 80 90 100k 1m 10m 100m v out /v in db figure 15. frequency response of 1 mhz low-pass filter high common-mode-output-impedance ampli?r changing the connection to v ocm (pin 2) can change the common-mode from low impedance to high impedance. if v ocm is actively set to a particular voltage, the ad8132 will try to force v out,cm to the same voltage with a relatively low output impedance. all the previous analysis assumed that this output impedance is arbitrarily low enough to drive the load condition in the circuit. however, the are some applications that bene t from a high common-mode output impedance. this can be accomplished with the circuit shown in figure 16. r g 348 r f 348 r f 348 r g 348 10 10 1k 1k 49.9 49.9 figure 16. high common-mode output impedance differ- ential ampli?er the complementary electrical elds will mostly be con ned to the space between the two twisted conductors and will not sig- ni cantly radiate out from the cable. the current in the cable will create magnetic elds that will radiate to some degree. however, the amount of radiation is mitigated by the twists, because for each twist, the two adjacent twists will have an opposite polarity magnetic eld. if the twist pitch is tight enough, these small magnetic eld loops will contain most of the magnetic flux, and the magnetic far- eld strength will be negligible. any imbalance in the differential drive signal will appear as a common-mode signal on the cable. this is the equivalent of a single wire that is driven with the common-mode signal. in this case, the wire will act as an antenna and radiate. thus, in order to minimize radiation when driving differential twisted pair cables, the differential drive signal should be very well balanced. the common-mode feedback loop in the ad8132 helps to minimize the amount of common-mode voltage at the output, and can therefore be used to create a well-balanced differential line driver. figure 11 shows an application that uses an ad8132 as a balanced line driver and ad830 as a differential receiver con gured for unity gain. this circuit was operated with 10 m of category 5 cable. transmit equalizer any length of transmission line will attenuate the signals it carries. this effect is worse at higher frequencies than at low frequen- cies. one way to compensate for this is to provide an equalizer circuit that boosts the higher frequencies in the transmitter circuit, so that at the receive end of the cable, the attenuation effects are diminished. by lowering the impedance of the r g component of the feed- back network at higher frequency, the gain can be increased at high frequency. figure 12 shows a gain-of-two line driver that has its r g s shunted by 10 pf resistors. the effect of this is shown in the frequency response plot of figure 13. 249 49.9 10pf 499 10pf 249 24.9 v in 49.9 499 49.9 100 v out figure 12. frequency boost circuit 1 1000 20 10 0 10 20 30 40 50 60 70 80 v out /v in db 10 100 frequency mhz figure 13. frequency response for transmit boost circuit
rev. 0 ad8132 C19C v ocm is driven by a resistor divider that measures the output common- m ode voltage. thus, the common-mode output volt- age takes on the value that is set by the driven circuit. in this case it comes from the center point of the termination at the receive end of a 10 m length of category 5 twisted pair cable. if the receive end common-mode voltage is set to ground, it will be well-de ned at the receive end. any common-mode signal that is picked up over the cable length due to noise, will appear at the transmit end, and must be absorbed by the transmitter. thus, it is important that the transmitter have adequate common-mode output range to absorb the full ampli- tude of the common-mode signal coupled onto the cable and thus prevent clipping. another way to look at this is that the circuit performs what is sometimes called transformer action. one main difference is that the ad8132 passes dc while transformers do not. a transformer can also be easily con gured to have either a high or low common-mode output impedance. if the transformer s center tap is connected to a solid voltage reference, it will set the common-mode voltage on the secondary side of the transfo rmer. in this case, if one of the differential outputs is grounded, the other output will have only half of the differential output signal. this keeps the common-mode voltage at ground, where it is required to be due to the center tap connection. this is analo- gous to the ad8132 operating with a low output impedance common-mode. see figure 17. v diff v ocm figure 17. transformer whose low output impedance secondary is set at v ocm if the center tap of the secondary of a transformer is allowed to float (or there is no center tap), the transformer will have a high common-mode output impedance. this means that the common- mode of the secondary will be determined by what it is connected to, and not by anything to do with the transformer itself. if one of the differential ends of the transformer is grounded, the other end will swing with the full output voltage. this means that the common-mode of the output voltage is one-half of the differential output voltage. but this shows that the common-mode is not forced via a low impedance to a given voltage. the common- mode output voltage can easily be changed to any voltage through its other output terminals. the ad8132 can exhibit the same performance when one of the outputs in figure 16 is grounded. the other output will swing at the full differential output voltage. the common-mode signal is measured by the voltage divider across the outputs and input to v ocm . this then drives v out,cm to the same level. at higher frequencies, it is important to minimize the capacitance on the v ocm node or else phase shifts can compromise the performance. the voltage divider resistances can also be lowered for better frequency response. v diff v ocm figure 18. transformer with high output impedance secondary full-wave recti?r the balanced outputs of the ad8132, along with a couple of schottky diodes, can create a very high-speed full-wave recti er. such circuits are useful for measuring ac voltages and other computational tasks. figure 19 shows the con guration of such a circuit. each of the ad8132 outputs drives the anode of an hp 2835 schottky diode. these schottky diodes were chosen for their high-speed opera- tion. at lower frequencies (approximately lower than 10 mhz), a silicon signal diode, like a 1n4148 can be used. the cathodes of the two diodes are connected together and this output node is connected to ground by a 50 ? resistor. r g1 348 r f1 348 r f2 348 r g2 348 +5v 5v r l 100 r t2 24.9 r t1 49.9 v in hp2835 v out 5v cr1 10k figure 19. full-wave recti?er the diodes should be operated such that they are slightly forward- biased when the differential output voltage is zero. for the schottky diodes, this is about 400 mv. the forward biasing can be conveniently adjusted by cr1, which, in this circuit, raises and lowers v out,cm without creating a differential output voltage. one advantage of this circuit is that the feedback loop is never momentarily opened while the diodes reverse their polarity within the loop. this is the scheme that is sometimes used for full-wave recti ers that use conventional op amps. these con ventional circuits do not work well at frequencies above about 1 mhz. if there is not enough forward bias (v out,cm too low), the lower sharp cusps of the full-wave recti ed output waveform will be rounded off. also, as the frequency increases, there tends to be some rounding of the lower cusps. the forward bias can be increased to yield sharper cusps at higher frequencies. there is not a reliable, entirely quanti able, means to measure the performance of a full-wave recti er. since the ideal wave- form has periodic sharp discontinuities, it should have (mostly even) harmonics that have no upper bound on the frequency. however, for a practical circuit, as the frequency increases, the higher harmonics become attenuated and the sharp cusps that are present at low frequencies become signi cantly rounded.
rev. 0 C20C c3846C8C4/00 (rev. 0) 01035 printed in u.s.a. ad8132 outline dimensions dimensions shown in inches and (mm). 8-lead soic (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 8-lead microsoic (sm-8) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) the circuit was run at a frequency up to 300 mhz and, while it was still functional, the major harmonic that remained in the o utput was the second. this made it look like a sine wave at 600 mhz. f igure 20 is an oscilloscope plot of the output when driven by a 100 mhz, 2.5 v p-p input. sometimes a second harmonic generator is actually useful, as for creating a clock to oversample a dac by a factor of two. if the output of this circuit is run through a low-pass lter, it can be used as a second harmonic generator. 100mv 2ns 1v figure 20. full-wave recti?er response with 100 mhz input

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